Conventional electronic products are equipped with various electronic devices characterized by versatility and intricate electronic circuits and devices. Due to the ever-increasing demand for computation power, data processing speed, and storage capacity of electronic products, it is desirable to integrate as many semiconductor devices as possible on a chip. In addition, it is also desirable to pack as many chips as possible in Today's electronic products.
A 3D-stack chip package has been disclosed; mostly a plurality of memory chips of same or different kinds, such as DRAM, SRAM, and Flash chips have been stacked for such applications. Through-silicon-vias (or TSB's) have been used to form interconnects for these stacked chips. Furthermore, processors, logics and more memory chips have also been stacked in the 3D packaging structure in a similar manner. However, such 3D-stack packaging has some fatal disadvantages, mainly whenever any one of the stacking-chip fails, the whole package must be discarded. There is almost no reparability for this kind of 3D-stack chip package.
Another 3D packaging technology disclosed utilizes a folding-up technique. After folding a foldable material, a cubic or a pyramid shaped structure is formed which comprises a plurality of circuit surfaces. In between any two adjacent circuit surfaces exists a folding portion. The electrical interconnect among these different circuit surfaces are achieved by providing wires across the folding portions. Nonetheless, such wirings across the folding portions are done prior to the folding process. This folding-up technique package can only be used for low speed operations because there is no interconnects can be formed between adjacent circuit surfaces without a folding portion. In order for them to be interconnected, the wire must be routed with extra distance.
One more 3D packaging structure has been disclosed by folding and stacking a plurality of flexible circuit boards on a substrate. Such fold-and-stack 3D packaging technology suffers similar problems as those of the conventional 3D stack chips, for example, poor thermal dissipation, incapable of subsequent inspection, lack of reparability. Moreover, the signal integrity is also a concern due to significant interference between the electronic devices which are closely mounted on top of each other.
In view of this, there is a sufficient room for improvement in terms of 3D packaging structure design, for example, how to overcome overly long circuit wire paths, how to minimize signal interference, improve thermal dissipation, repair a defective chip, etc. Microelectronic 3D packaging structures and methods disclosed here are directed to addressing one or more of the problems set forth above.